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femtoclock? crystal-to- lvpecl/lvds/lvcmos clock generator ICS843S2807 idt ? / ics ? lvpecl/lvds/lvcmos clock generator 1 ICS843S2807by rev. a january 30, 2008 preliminary g eneral d escription ICS843S2807 is a low phase noise clock generator and is a member of the hiperclocks? family of high performance clock solutions from idt. the device provides five banks of outputs and a reference clock. the banks can be enabled by using a common output enable pin. a 25mhz crystal is used to generate the 50mhz, 66.67mhz, 87.5mhz, 100mhz, 125mhz, 133mhz and 350mhz frequencies. f eatures ? five banks of outputs: bank a: one single-ended (qa0) lvcmos output at: 133mhz and one (qa1/nqa1) lvpecl output at: 66.67mhz, 100mhz and 125mhz bank b: two (qb0, qb1) lvcmos outputs at: 50mhz bank c: one (qc0/nqc0) differential lvpecl output at: 87.5mhz bank d: one (qd0/nqd0) differential lvds output at: 350mhz one single-ended lvcmos reference clock output at: 25mhz ? crystal input frequency: 25mhz ? maximum output frequency: 350mhz ? 5% frequency margining ? full 3.3v operating supply ? 0c to 70c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs6) packages hiperclocks? ic s b lock d iagram osc phase detector vco 700mhz 28 14 2 8 ref_out qa0 qb0 qb1 qc0 nqc0 nqd0 qd0 nqa1 qa1 25mhz xtal_in xtal_out f_sel[1:0] margin margin_mode reset oe 5.6, 7, 10.5 5.2631 2 lvcmos - 25mhz lvcmos - 133mhz lvcmos - 50mhz lvpecl - 87.5mhz lvpecl - 66.67/100 / 125mhz lvds - 350mhz pll_bypass 5% frequency margining 1 0 pullup pulldown pulldown pulldown pulldown pullup p in a ssignment 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 ICS843S2807 32-lead lqfp 7mm x 7mm x 1.4mm package body y package top view v cc qa1 nqa1 v cca 1 v ee qc0 nqc0 v cc f_sel0 f_sel1 v cc xtal_in xtal_out v ee v cca 2 reset oe margin margin_mode pll_bypass v ee qd0 nqd0 v cc v ee ref_out v cco _ lvcmos qb0 qb1 v ee qa0 v cco _ lvcmos the preliminary information presented herein represents a product in pre-production. the noted characteristics are based on ini tial product characterization and/or qualification. integrated device technology, incorporated (idt) reserves the right to change any circuitry or specificat ions without notice.
idt ? / ics ? lvpecl/lvds/lvcmos clock generator 2 ICS843S2807by rev. a january 30, 2008 ICS843S2807 femtoclock? crystal-to-lvpecl/lvds/l vcmos clock generato r preliminary t able 1. p in d escriptions t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p c d p r e w o p e c n a t i c a p a c n o i t a p i s s i d , 0 a q , 1 b q , 0 b q t u o _ f e r v c c v , s o m c v l _ o c c v 5 6 4 . 3 = d b tf p r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r t u o e c n a d e p m i t u p t u o , 0 a q , 1 b q , 0 b q t u o _ f e r v s o m c v l _ o c c v 5 6 4 . 3 =5 1 r e b m u ne m a ne p y tn o i t p i r c s e d , 1 2 , 0 l e s _ f 1 l e s _ f t u p n ip u l l u p . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s n i p t c e l e s y c n e u q e r f . a 3 e l b a t e e s 4 2 , 7 1 , 6 1 , 3v c c r e w o p. s n i p y l p p u s e r o c , 4 5 , n i _ l a t x t u o _ l a t x t u p n i . t u p t u o e h t s i t u o _ l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c . t u p n i e h t s i n i _ l a t x , 3 1 , 6 2 3 , 7 2 , 0 2 v e e r e w o p. s n i p y l p p u s e v i t a g e n 1 2 , 7v , 2 a c c v 1 a c c r e w o p. s n i p y l p p u s g o l a n a 8t e s e rt u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . l l p d n a s r e d i v i d e h t s t e s e r 9e ot u p n ip u l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . n i p e l b a n e t u p t u o 0 1n i g r a mt u p n in w o d l l u p . e d o m l a m r o n d n a n i g r a m e h t n e e w t e b s t c e l e s . b 3 e l b a t e e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l 1 1e d o m _ n i g r a mt u p n in w o d l l u p . n i g r a m % 5 n e e w t e b s t c e l e s . b 3 e l b a t e e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l 2 1s s a p y b _ l l pt u p n in w o d l l u p . s r e d i v i d e h t o t t u p n i e h t s a l a t x d n a l l p e h t n e e w t e b s t c e l e s . l a t x s t c e l e s , h g i h n e h w . l l p s t c e l e s , w o l n e h w . s l e v e l e c a f r e t n i l t t v l / s o m c v l 5 1 , 4 10 d q n , 0 d qt u p t u o . s l e v e l e c a f r e t n i s d v l . s t u p t u o k c o l c d k n a b l a i t n e r e f f i d 9 1 , 8 10 c q , 0 c q nt u p t u o . s l e v e l e c a f r e t n i l c e p v l . s t u p t u o k c o l c c k n a b l a i t n e r e f f i d 3 2 , 2 21 a q , 1 a q nt u p t u o . s l e v e l e c a f r e t n i l c e p v l . s t u p t u o k c o l c a k n a b l a i t n e r e f f i d 0 3 , 5 2v s o m c v l _ o c c r e w o p. s t u p t u o l t t v l / s o m c v l r o f s n i p y l p p u s t u p t u o 6 20 a qt u p t u o . t u p t u o k c o l c a k n a b d e d n e - e l g n i s 5 1 . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e c n a d e p m i 9 2 , 8 20 b q , 1 b qt u p t u o . s t u p t u o k c o l c b k n a b d e d n e - e l g n i s 5 1 . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e c n a d e p m i 1 3t u o _ f e rt u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p t u o k c o l c e c n e r e f e r 5 1 . e c n a d e p m i : e t o n n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t s r e f e r
idt ? / ics ? lvpecl/lvds/lvcmos clock generator 3 ICS843S2807by rev. a january 30, 2008 ICS843S2807 femtoclock? crystal-to-lvpecl/lvds/l vcmos clock generato r preliminary t able 3a. f_sel x f unction t able s t u p n i n o i t a r e p o n i g r a me d o m _ n i g r a m 01% 5 - x0 l a n i m o n 11% 5 + t able 3b. margin/margin_mode f unction t able s t u p n i y c n e u q e r f t u p t u o 1 a q ) z h m ( 1 l e s _ f0 l e s _ f 01 0 0 1 10 5 2 1 11 ) t l u a f e d ( 7 6 . 6 6 a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o (lvcmos) -0.5v to v cco_lvcmos + 0.5v outputs, i o (lvds) contin uous current 10ma surge current 15ma outputs, i o (lvpecl) contin uous current 50ma surge current 100ma package thermal impedance, ja 71.9c/w (0 mps) junction-to-case storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. t able 4a. p ower s upply dc c haracteristics , v cc = v cco_lvcmos = 3.3v 5%,t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n av c c i ? a c c 0 1 * 3 . 3v c c v v s o m c v l _ o c c e g a t l o v y l p p u s t u p t u o5 3 1 . 3v 3 . 35 6 4 . 3v i e e t n e r r u c y l p p u s r e w o p d b ta m i a c c t n e r r u c y l p p u s g o l a n a d b ta m
idt ? / ics ? lvpecl/lvds/lvcmos clock generator 4 ICS843S2807by rev. a january 30, 2008 ICS843S2807 femtoclock? crystal-to-lvpecl/lvds/l vcmos clock generato r preliminary t able 4b. lvcmos/lvttl dc c haracteristics , v cc = v cco_lvcmos = 3.3v 5%,t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v c c 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t u p n i t n e r r u c h g i h , s s a p y b _ l l p , n i g r a m , t e s e r e d o m _ n i g r a m v c c v = n i v 5 6 4 . 3 =0 5 1a ] 0 : 1 [ l e s _ f , e o 5a i l i t u p n i t n e r r u c w o l , s s a p y b _ l l p , n i g r a m , t e s e r e d o m _ n i g r a m v c c v , v 5 6 4 . 3 = n i v 0 =5 -a ] 0 : 1 [ l e s _ f , e o0 5 1 -a v h o t u p t u o 1 e t o n ; e g a t l o v h g i h , t u o _ f e r 1 b q , 0 b q , 0 a q v s o m c v l _ o c c 5 6 4 . 3 =v% 5 6 . 2v v l o t u p t u o 1 e t o n ; e g a t l o v w o l , t u o _ f e r 1 b q , 0 b q , 0 a q v s o m c v l _ o c c 5 6 4 . 3 =v% 5 5 . 0v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n o tv s o m c v l _ o c c , n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . 2 / . m a r g a i d t i u c r i c t s e t d a o l t u p t u o t able 4c. lvds dc c haracteristics , v cc = 3.3v 5%,t a = 0c to 70c t able 5. c rystal c haracteristics r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 5 2z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 e c n a t i c a p a c t n u h s 7f p l e v e l e v i r d 1w m . l a t s y r c t n a n o s e r l e l l a r a p f p 8 1 n a g n i s u d e z i r e t c a r a h c : e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d o e g a t l o v t u p t u o l a i t n e r e f f i d 0 0 4v m v d o v d o e g n a h c e d u t i n g a m 0 5v m v s o e g a t l o v t e s f f o 5 2 . 1v v s o v s o e g n a h c e d u t i n g a m 0 5v m t able 4d. lvpecl dc c haracteristics , v cc = 3.3v 5%,t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov c c 4 . 1 -v c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov c c 0 . 2 -v c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t c c . v 2 -
idt ? / ics ? lvpecl/lvds/lvcmos clock generator 5 ICS843S2807by rev. a january 30, 2008 ICS843S2807 femtoclock? crystal-to-lvpecl/lvds/l vcmos clock generato r preliminary t able 6. ac c haracteristics , v cc = v cco_lvcmos = 3.3v 5%,t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 0 d q n / 0 d q0 5 3z h m 0 a q3 3 1z h m 1 a q n / 1 a q1 = 0 l e s _ f , 1 = 1 l e s _ f7 6 . 6 6z h m 1 a q n / 1 a q1 = 0 l e s _ f , 0 = 1 l e s _ f0 0 1z h m 1 a q n / 1 a q0 = 0 l e s _ f , 1 = 1 l e s _ f5 2 1z h m 1 b q , 0 b q0 5z h m 0 c q n / 0 c q5 . 7 8z h m t u o _ f e r5 2z h m t ) b ( k s ; w e k s k n a b 2 , 1 e t o n 1 b q , 0 b qd b ts p t ) c c ( t i j e l c y c - o t - e l c y c 2 e t o n ; r e t t i j t u o _ f e r5 7s p 0 a q0 5 1s p 1 b q , 0 b q5 7s p 1 a q n / 1 a q0 0 2s p 0 c q n / 0 c q0 5s p 0 d q n / 0 d q0 5s p t r t / f t u p t u o e m i t l l a f / e s i r , t u o _ f e r 1 b q , 0 b q , 0 a q % 0 8 o t % 0 20 5 3s p , 1 a q n / 1 a q 0 c q n / 0 c q % 0 8 o t % 0 20 5 2s p 0 d q n / 0 d q% 0 8 o t % 0 20 0 4s p c d oe l c y c y t u d t u p t u o , t u o _ f e r 1 b q , 0 b q , 0 a q 5 45 5% , 1 a q n / 1 a q 0 c q n / 0 c q 5 45 5% 0 d q n / 0 d q5 45 5% . s n o i t i d n o c d a o l l a u q e h t i w d n a s e g a t l o v e m a s e h t t a s t u p t u o f o k n a b a n i h t i w w e k s s a d e n i f e d : 1 e t o n . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 2 e t o n
idt ? / ics ? lvpecl/lvds/lvcmos clock generator 6 ICS843S2807by rev. a january 30, 2008 ICS843S2807 femtoclock? crystal-to-lvpecl/lvds/l vcmos clock generato r preliminary 3.3v lvds o utput l oad ac t est c ircuit 3.3v lvcmos o utput l oad ac t est c ircuit lvcmos b ank s kew p arameter m easurement i nformation 3.3v lvpecl o utput l oad ac t est c ircuit scope qx nqx 3.3v5% power supply +? float gnd lvds scope qx lvcmos gnd 1.65v5% -1.65v5% v cc , v cco_lvcmos 1.65v5% v cca1, v cca2 v cc v cca1, v cca2 t sk(b) v cco 2 v cco 2 qbx qbx lvcmos o utput d uty c ycle /p ulse w idth /p eriod d ifferential o utput d uty c ycle /p ulse w idth /p eriod scope qx nqx lvpecl v ee 2v -1.3v 0.165v v cc 2v t pw t period t pw t period odc = x 100% nqa1, nqc0, nqd0 qa1, qc0, qd0 t period t pw t period odc = x 100% t pw qa0, qb0, qb1, ref_out v cca1, v cca2
idt ? / ics ? lvpecl/lvds/lvcmos clock generator 7 ICS843S2807by rev. a january 30, 2008 ICS843S2807 femtoclock? crystal-to-lvpecl/lvds/l vcmos clock generato r preliminary lvpecl o utput r ise /f all t ime out out lvds dc input ? ? ? v os / v os v ddo_lvds clock outputs 20% 80% 80% 20% t r t f clock outputs 20% 80% 80% 20% t r t f v od d ifferential o utput v oltage s etup ? ? ? 100 out out lvds dc input v od / v od v dd clock outputs 20% 80% 80% 20% t r t f v swing o ffset v oltage s etup lvcmos o utput r ise /f all t ime lvds o utput r ise /f all t ime phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power rms p hase j itter p arameter m easurement i nformation , continued
idt ? / ics ? lvpecl/lvds/lvcmos clock generator 8 ICS843S2807by rev. a january 30, 2008 ICS843S2807 femtoclock? crystal-to-lvpecl/lvds/l vcmos clock generato r preliminary a pplication i nformation p ower s upply f iltering t echniques f igure 1. p ower s upply f iltering 10 v cca 10 f .01 f 3.3v .01 f v cc c rystal i nput i nterface the ICS843S2807 has been characterized with 18pf parallel resonant crystals. the capacitor values shown in figure 2 below f igure 2. c rystal i npu t i nterface were determined using a 25mhz crystal and were chosen to minimize the ppm error. i nputs : lvcmos c ontrol p ins all control pins have internal pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvcmos o utputs all unused lvcmos output can be left floating. there should be no trace attached. lvds o utputs all unused lvds output pairs can be either left floating or terminated with 100 across. if they are left floating, we recommend that there is no trace attached. lvpecl o utputs all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. xtal_in xtal_out x1 18pf parallel crystal c1 14p c2 14p as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter perfor- mance, power supply isolation is required. the ICS843S2807 pro- vides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc , v cca1, v cca2 and v cco should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v cc pin and also shows that v cca requires that an additional 10 resistor along with a 10f bypass capacitor be connected to the v cca pin.
idt ? / ics ? lvpecl/lvds/lvcmos clock generator 9 ICS843S2807by rev. a january 30, 2008 ICS843S2807 femtoclock? crystal-to-lvpecl/lvds/l vcmos clock generato r preliminary lvcmos to xtal i nterface the xtal_in input can accept a single-ended lvcmos signal through an ac couple capacitor. a general interface diagram is shown in figure 3. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configuration requires that the output impedance of the driver f igure 3. g eneral d iagram for lvcmos d river to xtal i nput i nterface (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 applications, r1 and r2 can be 100 . this can also be accomplished by removing r1 and making r2 50 . r2 zo = 50 vdd ro zo = ro + rs r1 vdd xta l _ i n xta l _ o u t .1uf rs the receiver input. for a multiple lvds outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. lvds d river t ermination a general lvds interface is shown in figure 4. in a 100 differential transmission line environment, lvds drivers require a matched load termination of 100 across near f igure 4. t ypical lvds d river t ermination 100 ohm differiential transmission line r1 100 3.3v + - lvds_driv er 3.3v
idt ? / ics ? lvpecl/lvds/lvcmos clock generator 10 ICS843S2807by rev. a january 30, 2008 ICS843S2807 femtoclock? crystal-to-lvpecl/lvds/l vcmos clock generato r preliminary t ermination for 3.3v lvpecl o utputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are rec- ommended only as guidelines. fout and nfout are low impedance follower outputs that gen- erate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 f igure 5b. lvpecl o utput t ermination f igure 5a. lvpecl o utput t ermination transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal dis- tortion. figures 5a and 5b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board design- ers simulate to guarantee compatibility across all printed circuit and clock component process variations. v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin
idt ? / ics ? lvpecl/lvds/lvcmos clock generator 11 ICS843S2807by rev. a january 30, 2008 ICS843S2807 femtoclock? crystal-to-lvpecl/lvds/l vcmos clock generato r preliminary r eliability i nformation t ransistor c ount the transistor count for ICS843S2807 is: 11,230 t able 7. ja vs . a ir f low t able for 32 l ead lqfp ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 71.9c/w 62.1c/w 58.5c/w
idt ? / ics ? lvpecl/lvds/lvcmos clock generator 12 ICS843S2807by rev. a january 30, 2008 ICS843S2807 femtoclock? crystal-to-lvpecl/lvds/l vcmos clock generato r preliminary p ackage o utline - y s uffix for 32 l ead lqfp t able 8. p ackage d imensions reference document: jedec publication 95, ms-026 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s a b b m u m i n i ml a n i m o nm u m i x a m n 2 3 a - -- -0 6 . 1 1 a 5 0 . 0- -5 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 0 3 . 07 3 . 05 4 . 0 c 9 0 . 0- -0 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d . f e r 0 6 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e . f e r 0 6 . 5 e c i s a b 0 8 . 0 l 5 4 . 00 6 . 05 7 . 0 0 - - 7 c c c - -- -0 1 . 0
idt ? / ics ? lvpecl/lvds/lvcmos clock generator 13 ICS843S2807by rev. a january 30, 2008 ICS843S2807 femtoclock? crystal-to-lvpecl/lvds/l vcmos clock generato r preliminary while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature ranges, high reliability or other extraordina ry environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or w arrant any idt product for use in life support devices or critical medical instruments. t able 9. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t y b 7 0 8 2 s 3 4 8d b tp f q l d a e l 2 3y a r tc 0 7 o t c 0 t y b 7 0 8 2 s 3 4 8d b tp f q l d a e l 2 3l e e r & e p a t 0 0 0 1c 0 7 o t c 0 f l y b 7 0 8 2 s 3 4 8l b 7 0 8 2 s 3 4 s c ip f q l " e e r f - d a e l " d a e l 2 3y a r tc 0 7 o t c 0 t f l y b 7 0 8 2 s 3 4 8l b 7 0 8 2 s 3 4 s c ip f q l " e e r f - d a e l " d a e l 2 3l e e r & e p a t 0 0 0 1c 0 7 o t c 0 . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 ? 2008 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa ICS843S2807 femtoclock? crystal-to-lvpecl/lvds/l vcmos clock generato r preliminary corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia integrated device technology idt (s) pte. ltd. 1 kallang sector, #07-01/06 kolam ayer industrial park singapore 349276 +65 6 744 3356 +65 6 744 1764 (fax) europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 +44 (0) 1372 378851 (fax) japan nippon idt kk sanbancho tokyu bld. 7f, 8-1 sanbancho chiyoda-ku, tokyo 102-0075 +81 3 3221 9822 +81 3 3221 9824 (fax)

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